Systemverilog Cheat Sheet

| Posted on by



  • View SystemVerilog-Assertions-Checklist-Cheat-Sheet-v0.3.pdf from ELECTRICAL EC622 at Nirma University, Ahmedabad. SystemVerilog Assertions Checklist/Cheat Sheet.
  • Created Date: 8/9/2018 10:38:59 AM.

SystemVerilog is the first industry-standard language covering the requirements of both design and verification. It provides the benefits of broad capability in all areas of design and verification, with the advantage of a widely supported IEEE standard spanning project generations.

NOTE: This is a work in progress, please let us know via issue/gitter/emailif you'd like to see anything added to this.

This is inspired by the chisel cheatsheetand will be rendered in a similar single page layout soon.

Bit

  • m.Bit: boolean value
  • m.VCC, m.GND: boolean literals

Bits and Integers

  • m.Bits[N]: length N bit vector with bitwise logical operators defined
  • m.UInt[N]: length N unsigned integer that includes Bits operators and unsigned arithmetic (e.g. +, -, ...) and comparison operators (e.g. <, <=, ...)
  • m.SInt[N]: length N signed integer that includes Bits operators and signed arithmetic (e.g. +, -, ...) and comparison operators (e.g. <, <=, ...)

Array

  • m.Array[N, T]: fixed length array of length N containing values of type T with equality operator () defined

Tuples and Products

Verilog Pdf

  • m.Tuple[t0, t1, ...]: heterogenous compound data type containing members of type t0, t1, ... Values of such types can be indexed using integer keys like Python tuples (e.g. for a tuple value x, type(x[0]) t0).
  • m.Product.from_fields(name, dict(k0=t0, k1=t1, ...)): heterogenous compound data type containing members of type t0, t1, ... Values of such types can be indexed using attributes (e.g. for a product value x, type(x.k0) t0). name='anon' makes this type anonymous.
  • Alternate syntax: python class <name>(m.Product): k0 = t0 k1 = t1 ...

Enum

Statically typed enumerated type:

m.In(T), m.Out(T), m.InOut(T) qualify type T to be an input, output, andinout respectively.

Cheat
  • m.bits(value, n=None): convert value to an Bits (same rules as m.array except if the input is a magma type or list, the members must be convertible to a Bit (e.g. Bit, bool, 0, 1))
  • m.array(value, n=None): convert value to an array. value must be a magma type (Bit, Tuple, Array), a Python integer (e.g. literal), or a Python sequence (e.g. list). If n is None, the width of the array is inferred from value (e.g. length of the list, bit length of the integer, length of the magma type)
  • m.uint(value, n=None): convert value to an UInt (same rules as m.bits, except will not convert m.SInt to m.UInt)
  • m.sint(value, n=None): convert value to an SInt (same rules as m.bits, except will not convert m.UInt to m.SInt)

Contained in the module magma.math* m.math.log2_ceil(x: int) -> int: log2(x) rounded up* m.math.log2_floor(x: int) -> int: log2(x) rounded down* m.math.is_pow2(x: int) -> bool: True if x is a power of 2

Retain state until updated:

Define update value by wiring to the input I port

Set N to None for a Register of a single Bit (setting N to 1 willproduce a register of Bits[1])

  • height: number of elements
  • width: width of each element
  • readonly: ROM if True else RAM
  • read_latency: number of registers to append to read out port

Memory ports (where addr_width = max(clog2(height - 1), 1)):

  • RADDR: m.In(m.Bits[addr_width])
  • RDATA: m.Out(m.Bits[width])
  • WADDR: m.In(m.Bits[addr_width])
  • WDATA: m.In(m.Bits[width])
  • CLK: m.In(m.Clock)
  • WE: m.In(m.Bit)

Defining: subclass m.Circuit

Usage: circuits are used by instancing them inside another definitions and their ports are accessed using dot notation

Wiring: wire an output to an input using @= operator (statically typed)

Metaprogramming: abstract over parameters by generating a circuit definition inside a closure

Infix operators

All types support the following operators:- Equal - Not Equal !=

The Bit type supports the following logical operators.- And &- Or |- Exclusive or ^- Not ~

The Array type family supports the following operator.- Dynamic bit selection my_arry[add.O] (select a bit dynamically using a magma value).

Verilog Language Manual

The Bits type family supports the following logical operators.- And & (element-wise)- Or | (element-wise)- Exclusive or ^ (element-wise)- Not ~ (element-wise)- Logical right shift (with zeros) >>- Logical left shift (with zeros) <<

The UInt and SInt types support all the logical operatorsas well as arithmetic and comparison operators.- Add +- Subtract/Negate -- Multiply *- Divide /- Less than <- Less than or equal <=- Greater than >- Greater than or equal >=

Note that the the right shift operator when applied to an SInt becomesan arithmetic shift right operator (which replicates the sign bit as it shifts right).

Functional operators

  • mantle.mux(*I, S) (constraint: len(S) log2_ceil(len(I))): select I[S].
  • m.zext(v, n): zero extend array v by n
  • m.sext(v, n): sign extend array v by n
  • m.concat(*arrays): concat arrays together
  • m.repeat(value, n): create an array repeating valuen times

produces

See here for more details.

See here for more details.

For simple designs the major steps are:

  1. Compile the design
  2. Run the Simulation
  3. Generate Code Coverage Report

Compiling Verilog design using VCS

Included Options

  • -cm coverage-type: specifies the type of coverage information to collect. The line, tgl, cond, fsm and path options enable statement (line), toggle, condition, FSM, and path coverage respectively. Any combination of coverage can be enabled simultaneously using the + sign e.g. -cm cond+line enables conditional and line coverage.
  • -cm_line contassign: monitor continuous assignments for line coverage
  • -cm_cond allops+anywidth+event: monitor non-logical operators, of any width, and always block sensitivity expressions for condition coverage
  • -cm_noconst: try to automatically ignore constant expressions and unreachable statements
    for line and condition coverage
  • +lint=all: turns on all verilog warnings
  • +v2k: tells VCS to handle Verilog-2001 features, include this option if you are using those features
  • -PP: turns on support for using the VPD trace output format
  • -debug_all option allows to run the interactive DVE tool and use steps to debug the design
  • -l file_name: logs the compiler messages to given file name
  • -f file_name: tells VCS to read source files from the given file

Few optional arguments

  • -sverilog: include this options if system verilog source files are also present. This enables compilation for system verilog source files.
  • -v: use this flag to indicate which verilog files are part of the library and thus be compiled if needed.
  • -timescale: can be used to specify how the abstract delay units in their design map into real time units e.g. -timescale=1ns/10ps

During compilation a subdirectory named csrc is created to store the files generated by compilation. This directory includes:

  • Makefile for the compilation process
  • Object files from the compilation. These object files are linked to create the simv executable.
  • Intermediate C or Assembly source files.

Incremental Compilation

The source files are compiled on module-by-module basis. Incremental compilation means that if we run the vcs command again, only the modules that have changed after the last compilation are recompiled. VCS compares the modules in the source file to the descriptor information in the generated files from the last compilation, if a module’s contents are different from what VCS recorded in the last compilation, VCS recompiles the module.

Compile time options that affect incremental compilation all begin with -M.

Running the Simulation

For text based output use:

For debugging with DVE GUI use:

For Generating code coverage information run as:

Generating code coverage reports using VCS URG

For generating code coverage report in html form use the following command

To generate code coverage report in text form add the extra options as

Systemverilog Cheat Sheet

A directory named urgReport will be created in current directory. This directory contains all the generated reports.

References

Systemverilog Cheat Sheet

  • VCS Quickstart
  • VCS User Guide